1. Field of the Invention
The present invention relates to a semiconductor memory, and more specifically to a dynamic random access memory having an improved reading circuit.
2. Description of Related Art
With recent advancement of a microfabrication technology, the proportion of a "coupling capacitance between bit lines" included in a bit line capacitance is increasing. The "coupling capacitance between bit lines" will be called an "inter-bitline coupling capacitance" in this specification. In a DRAM (dynamic random access memory), the increase of this inter-bitline coupling capacitance reduces a potential difference between a pair of bit lines connected to the same sense amplifier. Here, the pair of bit lines includes a bit line to which data is outputted from a selected DRAM cell, and a bit line on which a reference potential is held. The potential difference between a pair of bit lines connected to the same sense amplifier will be called an "inter-bitline potential difference" in this specification.
First, the inter-bitline potential difference in a reading operation under an ideal condition having no inter-bitline coupling capacitance will be formulated. Referring to FIG. 1, there is shown a circuit diagram illustrating a portion of the construction of a prior art DRAM circuit.
In FIG. 1, a DRAM cell 100-1 and another DRAM cell 100-2 are respectively connected to a pair of bit lines BLT and BLN connected directly to the same sense amplifier 104, which is activated by a pair of complementary sense amplifier activation signals SAP and SAN. A gate of a switching transistor in the DRAM cell 100-1 is connected to a word line SWL1, and a gate of a switching transistor in the DRAM cell 100-2 is connected to another word line SWL2. The pair of bit lines BLT and BLN are precharged to a reference potential Vref by action of a precharge circuit 805 controlled by an activation signal PDL.
After the activation signal PDL is brought to a ground potential GND to deactivate the precharge circuit 805, for example, the word line SWL1 is brought to a potential Vboot so as to select the DRAM cell 100-1, so that data stored in the DRAM cell 100-1 is outputted to the bit line BLT. Here, assume that a capacitance in the DRAM cell is Cs, a bit line capacitance is Cb, and a potential in the DRAM cell is V1. On the other hand, an inter-bitline coupling capacitance Cc between the bit lines BLT and BLN is OfF (in the ideal condition in which the inter-bitline coupling capacitance is negligibly sufficiently small). In the reading operation, at this time, the potential of the bit line BLT changes from the reference potential Vref to {(Cs.multidot.V1+Cb.multidot.Vref)/(Cs+Cb)}. Since the other bit line BLN is maintained at the reference potential Vref, the potential difference (.vertline.VBLT-VBLN.vertline.) between the bit lines BLT and BLN is expressed as follows: EQU .vertline.VBLT-VBLN.vertline.={Cs/(Cs+Cb)}.multidot..vertline.V1-Vref.vertl ine. (1)
This potential difference expressed by the equation (1) is amplified by the sense amplifier 104.
The equation (1) is derived as follows: First, assume Cc=0fF in FIG. 1. Just before the word line SWL1 is brought to the high level potential Vboot, the capacitance and the potential of each of the bit lines BLT and BLN are Cb and Vref, so that the electric charge amount on each bit line is Cb.times.Vref, and on the other hand, the capacitance and the potential in the DRAM cell 100-1 are Cs and V1, so that the electric charge amount in the cell 100-1 is Cs.times.V1.
In this condition, if the word line SWL1 is brought to the high level potential Vboot to put the bit line BLT in a condition electrically connected to the DRAM cell 100-1, the potential of the bit line BLT becomes equal to the potential within the DRAM cell 100-1. Here, the potentials of the bit lines BLT and BLN after the bit line BLT and the DRAM cell 100-1 are electrically connected to each other, are called VBLT and VBLN, respectively. The electric charge amount on the bit line BLT is expressed as Cb.times.VBLT, the electric charge amount on the bit line BLN is expressed as Cb.times.VBLN, and the electric charge amount in the DRAM cell 100-1 is expressed as CS.times.VBLT.
Since the total electric charge amount of the bit line BLT and the DRAM cell 100-1 does not change, the following relation holds: EQU Cs.times.V1+Cb.times.Vref=Cb.times.VBLT+CS.times.VBLT
Accordingly, EQU VBLT=(Cs.times.V1+Cb.times.Vref)/(Cs+Cb) (2)
On the other hand, since the electric charge amount of the bit line BLN does not change, the following relation holds: EQU Cb.times.Vref=Cb.times.VBLN
Accordingly, EQU VBLN=Vref (3)
Thus, the equation (1) can be obtained by seeking a difference between the bit lines VBLT and VBLN from the equations (2) and (3).
A problem in the prior art is that with the increase of the inter-bitline coupling capacitance, the inter-bitline potential difference in the reading operation decreases, as mentioned hereinbefore. If the inter-bitline potential difference decreases, there occurs possibility that the potential difference cannot be properly amplified by the sense amplifier with the result that an erroneous information is outputted. In the following, why the inter-bitline potential difference decreases will be described with formulation.
The worst condition in the reading operation is that all the DRAM cells store the same data. Here, assume that the proportion of the inter-bitline coupling capacitance included in the bit line capacitance is "x", where 0.ltoreq.x&lt;1. Therefore, the coupling capacitance Cc is expressed as "x.multidot.Cb", and the bit line capacitance excluding the coupling capacitance is expressed as "(1-x).multidot.Cb".
Under this condition, the word line SWL1 is brought to the potential Vboot so that the data stored in the DRAM cell 100-1 is read out and outputted to the bit line BLT of the pair of bit lines which were precharged to the reference potential Vref. At this time, the potential VBLT of the bit line BLT is expressed by the following equation (4), and the potential VBLN of the bit line BLN changes to a potential expressed by the following equation (5) because of the coupling capacitance between the bit lines BLT and BLN. EQU VBLT={(1-x.sup.2).multidot.Cs.multidot.Vref+Cs.multidot.V1}/{(1-x.sup.2).mu ltidot.Cb+Cs} (4) EQU VBLN=[{(1-x.sup.2).multidot.Cb+(1-x)Cs}.multidot.Vref+x.multidot.Cs.multido t.V1]/{(1-x.sup.2).multidot.Cb+Cs} (5)
These equations (4) and (5) are derived as follows: First, assume Cc=x.multidot.Cb in FIG. 1 where 0&lt;x&lt;1. Just before the word line SWL1 is brought to the high level potential Vboot, the electric charge amount stored in the capacitance (1-x).multidot.Cb between the bit line BLT and a substrate is (1-x).multidot.Cb.times.Vref, and the electric charge amount stored in the capacitance x.multidot.Cb between the bit line BLT and the bit line BLN is x.multidot.Cb.times.(Vref-Vref)=0 (zero). In addition, the electric charge amount stored in the capacitance (1-x).multidot.Cb between the bit line BLN and the substrate is (1-x).multidot.Cb.times.Vref, and the electric charge amount stored in the capacitance x.multidot.Cb between the bit line BLN and the bit line BLT is x.multidot.Cb.times.(Vref-Vref)=0 (zero). The electric charge amount in the cell 100-1 is Cs.times.V1.
In this condition, if the word line SWL1 is brought to the high level potential Vboot to put the bit line BLT in a condition electrically connected to the DRAM cell 100-1, the potential of the bit line BLT becomes equal to the potential within the DRAM cell 100-1. Here, the potentials of the bit lines BLT and BLN after the bit line BLT and the DRAM cell 100-1 are electrically connected to each other, are called VBLT and VBLN., respectively. The electric charge amount stored in the capacitance (1-x).multidot.Cb between the bit line BLT and the substrate is (1-x).multidot.Cb.times.VBLT, and the electric charge amount stored in the capacitance x.multidot.Cb between the bit line BLT and the bit line BLN is x.multidot.Cb.times.(VBLT-BLN). In addition, the electric charge amount stored in the capacitance (1-x).multidot.Cb between the bit line BLN and the substrate is (1-x).multidot.Cb.times.VBLN, and the electric charge amount stored in the capacitance x.multidot.Cb between the bit line BLN and the bit line BLT is x.multidot.Cb.times.(VBLN-VBLT). The electric charge amount in the cell 100-1 is Cs.times.VBLT.
Since the total electric charge amount of the bit line BLT and the DRAM cell 100-1 does not change, the following relation holds: EQU (1-x)Cb.times.Vref+Cs.times.V1=(1-x)Cb.times.VBLT+x.multidot.Cb.times.(VBLT -VBLN)+Cs.times.VBLT (6)
Similarly, since the electric charge amount of the bit line BLN does not change, the following relation holds: EQU (1-x)Cb.times.Vref=(1-x)Cb.times.VBLN+x.multidot.Cb.times.(VBLN-VBLL)(7)
Thus, the equations (4) and (5) can be obtained by solving the equations (6) and (7) as simultaneous equations. By seeking a difference between the bit lines VBLT and VBLN from the equations (4) and (5), the potential difference .vertline.VBLT-VBLN.vertline. can be obtained as follows: EQU .vertline.VBLT-VBLN.vertline.=[Cs/{(1+x).multidot.Cb+Cs/(1-x)}].multidot..v ertline.V1-Vref.vertline. (8)
This equation is also true when the DRAM cell 100-2 is selected by bringing the word line SWL2 to the potential Vboot. In addition, assuming x=0, the equation (8) becomes the same as the equation (1). Respective coefficients (1+x) and 1/(1-x) for Cb and Cs included in the denominator are an increasing function for "x" (0.ltoreq.x&lt;1). Therefore, the equation (8) is a decreasing function for "x".
From the above mentioned relation, it is confirmed that the increase of the proportion "x" of the inter-bitline coupling capacitance will decrease the inter-bitline potential difference in the reading operation.
Japanese Patent Application Pre-examination Publication No. JP-A-10-069795 (an English abstract of which is available and the content of the English abstract is incorporated by reference in its entirety into this application) proposes to put a node at a reference potential side of the sense amplifier into a floating condition before the a selected word line is activated. However, this cannot solve the above mentioned problem of the prior art. Furthermore, Japanese Patent Application Pre-examination Publication No. JP-A-03-108187 (an English abstract of which is available and the content of the English abstract is incorporated by reference in its entirety into this application) proposes to vary the reference potential at the reading time. However, this cannot also solve the above mentioned problem of the prior art.